The present disclosure is related generally to methods for the preparation of a wafer surface, and in particular, to methods for the processing of nanostructures, for filling nanoscale holes and trenches, for removing voids in the fillings, and for planarizing a wafer surface
Both filling of nanoscale hole and trenches, and the planarizing of wafer surfaces are very important steps in integrated circuit fabrication, as well as in other nanoscale devices manufacturing. Currently, the filling of via holes and trenches is by chemical vapor deposition (CVD), physical depositions (such as sputtering, evaporation), atomic layer deposition (ALD), and chemical fluid deposition (CFD), etc. For example, in the CVD metal plug process for the interconnects of integrated circuits, the via holes and trenches are etched in a dielectric material, and subsequently filled up with a metal. Clearly, any voids left in the via holes or trenches caused by poor step coverage will create a serious problem for the interconnects. The step coverage of tungsten CVD is still limited by the low volatility of the precursor gas WF6 that leads to a low vapor pressure. The result is a mass transport limited deposition rate, and the hole openings receive faster deposition and may be closed before the volume of the holes are completely filled. Another disadvantage of CVD is its relatively high thermal budget.
Atomic layer deposition can achieve excellent step coverage in certain conditions. It is a modified form of CVD with gas precursors introduced one at a time and pump/purge in between, so that a film is deposited at the rate of one atomic layer per cycle, with a typical deposition rate of order 0.5 nm/min. Not only is the slow deposition rate a manufacturing issue, but also in ALD, voids may be formed if the via holes or trenches have sidewalls with negative angles.
Another candidate for filling future high aspect ratio via holes and trenches is chemical fluid deposition (CFD) which uses supercritical fluids like CO2 as a carrier for organometallics. As the supercritical fluid CO2 retains its gas nature and can flow into deep holes, the material deposition rate is limited by chemical reaction rate, giving conformal step-coverage. The drawbacks of CFD include high process pressure on the order of 100 bar, and limited choices of precursors having high solubility in the supercritical fluid. Moreover, like ALD, voids may be formed when via holes or trenches have negative sidewall angles.
In wafer planarization a traditional approach is to utilize a chemical mechanical polishing (CMP) method where chemical slurry is deposited on a wafer surface and subsequent polishing removes any non-flatness of the wafer. The process is messy, generating significant chemical and water waste.
Therefore, there is still a need for a new method capable of filling nanoscale via holes and trenches having high aspect ratios, regardless of the sidewall angles, and which has a high throughput. Similarly, there is a need for an efficient and clean method for wafer surface planarization.